Integrated circuit chips, such as magnetic random access memory (MRAM) chips, are typically encapsulated in protective packages that provide electrical connection pin or pads for soldering onto printed circuit boards. Magnetic random access memory (MRAM) based on magneto-resistive (MR) technologies, especially the magnetic tunnel junction (MTJ) based spin transfer torque magnetic random access memory (STT-MRAM), is regarded as next generation memory that has potential to replace many existing memory technologies (flash, DRAM, SRAM) and create new applications. A typical STT-MRAM MTJ) stack has a pinned reference layer whose magnetization is fixed in certain direction by either intrinsic anisotropy field, or through an exchange coupling field from an adjacent magnetic layer. It also has a switchable free layer, whose magnetization direction can be switched relative to that of the reference layer by an electric current flowing between the reference layer and free layer through an junction layer, typically an oxide of Mg, Al and Ti, or a metallic layer of Cu, Au, or Ag. Different relative angles of the magnetization directions between the free layer and reference layer result in different resistance levels across the MTJ stack. Thus, by switching the free layer magnetization directions with the electric current, an STT-MRAM can be switched into high and low resistance states that are persistent and can be used to represent data bits.
However, due to the free layer being a layer made of magnetic material, it can also be switched or perturbed by an externally applied magnetic field, when the field strength is strong enough (e.g. 100 Gauss or higher). Therefore, shielding is generally required for STT-MRAM product to function properly as a data storage device without being perturbed or erased by unwanted external fields from the environment. Typically one or more magnetic shields shaped into blocks or sheets are positioned close to STT-MRAM chip in the chip-packaging process. The shields, under the external magnetic fields, are supposed to produce a counteracting field at the MTJ locations of the MRAM chip and reduce the total field on the MTJ. The chip should experience a weaker effective field than the external field applied to the MRAM product and perturbation is reduced. However, the prior art has limited success in shielding packaged MRAM products.
Because shielding must not conflict with the bonding wires, single or multiple sheet shields can be positioned too far away from the MRAM chip, so that the shield effect is degraded seriously by the distance between shield and chip's MTJ baring surface (U.S. Pat. No. 4,953,002, U.S. Pat. No. 5,939,772, U.S. Pat. No. 6,906,396, U.S. Pat. No. 7,459,769).
Partial-wrap-around or full-wrap-around shield can cause additional cost and difficulty in the packaging process. (U.S. Pat. No. 5,561,265, U.S. Pat. No. 7,183,617, U.S. Pat. No. 6,936,763, U.S. Pat. No. 7,545,662, U.S. Pat. No. 7,687,283, U.S. Pat. No. 7,772,679).
Coating or electro-depositing the shield material onto chip or wafer surface adds additional cost for wafer manufacturing and does not allow for sufficiently large thickness magnetic material (generally <100 um thickness) to produce a high enough cancelling field at MTJ. (U.S. Pat. No. 8,125,057, U.S. Pat. No. 5,902,690, U.S. Pat. No. 6,936,763, U.S. Pat. No. 6,627,932, U.S. Pat. No. 7,598,596, U.S. Pat. No. 7,545,662, U.S. Pat. No. 7,772,679).
When the shield's largest physical dimension is smaller than the MRAM chip size, this limits the cancelling field being generated at the edge of the chip and thus limits the area of the chip that can be used for MRAM data storage MTJ cells.
What is needed is a shield design that can a) position a large volume soft-magnetic shielding material with size being able to cover the largest physical size of the MRAM chip; b) with minimal distance to the MTJ bearing surface of the MRAM chip; and c) at same time, being achievable at chip-packaging step and with low cost.
FIGS. 1A and 1B will be used to discuss how magnetic shielding works. MRAM Chip 10 is subjected to applied magnetic field flux 11. When MRAM chip is exposed to an external magnetic field, the magnetic field may perturb or even erase the stored information by rotating or switching the magnetization of the data storage layer, i.e. free layer, of the MTJ cell. To reduce the undesired effect of the magnetic field on the MTJ cell, magnetically soft shielding 12 is used to reduce the effective field that is acting on the MRAM chip. The soft magnetic shield is easily magnetized by the applied field and shield magnetization is aligned in the same direction as the applied field. The magnetization of the shield produces positive and negative magnetic charges 13 on the two opposite ends of the shield. These positive and negative magnetic charges on the surface of the shield produce a magnetic field outside the shield body, which acts against the external applied magnetic field magnetization.
The effect of combining the applied magnetic field and the field generated by the shield magnetization is that the magnetic flux, whose spatial density reflects the magnetic field strength, is concentrated and conducted by the shield material. Space close to the shield material is effectively depleted of the magnetic field. Positioning an MRAM chip close to the shield material can help reduce the effective magnetic field that the chip is experiencing under a given applied magnetic field. The wire-bonding surface of the MRAM chip is usually the MTJ bearing surface. This surface needs to be as close to the shielding material as possible. The shield material size needs to be substantial large enough, especially in thickness, to attract enough magnetic flux and provide effective shielding. Shield thickness is preferably larger than the thickness of the MRAM chip thickness, and typically, 0.1 mm to a few millimeters. However, shield deposition in the wafer process cannot achieve such thickness economically or practically. By positioning an MRAM chip in between two shielding blocks, effective shielding can be further enhanced. However, enhancement is still dependent on the volume and size of the shields and the distance from shield to MRAM chip. If the shield is too thin or too far away from the MRAM chip, it fails to adequately shield. The preferred position of MRAM chip is always as close to the shield as possible.
Alternatively, a full wrap-around shield can effectively shield the MRAM chip from a field that has reasonable amplitude (less than 1k Gauss). But the cost associated with realizing a full wrap-around shield is high and may prove impractical for commercial products.
What is needed is a shield design that can position a large volume of magnetically soft shielding material over an area large enough to cover the largest physical size of the MRAM chip. The thickness should be no thinner than the MRAM chip itself, and there should be minimal distance to the MTJ bearing surface of the MRAM chip. The fabrication of the shield should be achievable at chip-packaging step and with low cost.